A quantum error correction benchmark tests how well a processor handles operations used to detect and correct qubit errors. A preprint submitted to arXiv on October 5, 2026, proposes one such test and compares 10 quantum processing units (QPUs) from IBM, IQM and Quantinuum. It uses circuits shaped around error-correction codes to assess processor behavior before logical-memory experiments.
A benchmark for operations quantum error correction needs
Quantum error correction (QEC) uses repeated checks to detect errors in fragile quantum information. Those workloads rely on operations such as mid-circuit measurements (MCM), which read part of a circuit while it is still running. A processor’s ability to handle these operations matters because QEC requires more than running gates: measurements and other steps must fit into the circuit’s sequence.
The proposed benchmark is called LR-QAOA, a fixed-parameter form of the quantum approximate optimization algorithm. It adapts that algorithm to circuits built from the check structure of a selected QEC code, giving the test patterns related to syndrome extraction—the process of gathering information used to identify errors.
How LR-QAOA turns circuit behavior into a signal
The benchmark tracks the algorithm’s approximation ratio, r, as circuit depth increases. The ratio represents the quality of the algorithm’s result; its decline across deeper circuits is the signal the method uses to assess hardware behavior. Circuit depth plays a role analogous to repeating rounds of syndrome extraction in a QEC experiment.
The method maps that decline to an effective hardware error, expressed as an equivalent two-qubit depolarizing rate, λ_eff. In plain terms, the test turns the changing quality of a code-structured workload into a measure that can be used to compare how processors handle it.
What the measurement and qubit counts mean
The overall comparison includes circuits with up to 2,950 MCM operations. A separate set of code-structured runs on Quantinuum’s Helios-1 and H2-1 uses up to 480 MCM operations.
Those runs cover several code structures: surface-code Hamiltonians reach up to 81 data qubits, triangular color-code Hamiltonians up to 91, and bivariate-bicycle qLDPC Hamiltonians up to 48. The figures describe the widths of benchmark circuits built to exercise QEC-like operations; they are not demonstrations of completed error correction at those sizes.
The comparison with logical memory on ibm_phoenix
The preprint also compares a surface-code LR-QAOA response with logical-memory experiment results across regions of IBM’s ibm_phoenix processor. It reports a correlation between the benchmark response and logical-memory performance in that regional comparison.
That gives the proposed test a concrete point of contact with logical-memory behavior, while keeping the result tied to the regions and processor examined.
