A Sina Finance report reproducing coverage from IT之家 says UltraRISC announced the UR-CP400 at the sixth RISC-V China Summit in 2026 as processor-core IP, a design that can be licensed for use in a chip. It is not a finished processor. The report says customer delivery of the IP is planned for Q1 2027.

The reported architecture and benchmark

The report describes the UR-CP400 as compliant with RVA23 and supporting RVV 1.0, the RISC-V vector extension. It gives the core an eight-issue, out-of-order design and a 14-stage pipeline.

The reported SPECint_base2006 result is above 22/GHz in an FPGA simulation configuration. That figure describes the stated simulation setup, rather than performance measured on production silicon.

The same report says the design includes virtualization enhancements aimed at multi-layer cloud environments and hardware-design optimization for agentic AI.

UltraRISC’s business and delivery plan

UltraRISC says it is headquartered in Shanghai. Its broader business includes processor IP, licensing, UltraRISC-branded processors, and core and SoC customization.

Customer delivery of the UR-CP400 processor-core IP is planned for Q1 2027.