Samsung Electronics shares reportedly fell 3.5% and SK Hynix shares 2.2% in South Korea on 11 September 2026 after reports that DeepSeek’s AI models require less high-bandwidth memory, or HBM. The market reaction is real; the bigger conclusion—that DeepSeek has permanently reduced global HBM demand—is not supported by the technical picture.
What DeepSeek’s work actually shows is narrower and more interesting: several architectural techniques can reduce the memory pressure created by inference, especially the attention data known as the KV cache. That is not the same thing as removing HBM from an AI system.
Why Samsung Electronics and SK Hynix shares fell
The reported share declines came after news that DeepSeek was using less HBM. For investors, the concern is straightforward: if each AI request needs less expensive, high-bandwidth memory, chipmakers could eventually sell less of it.
That interpretation jumps from a model-level efficiency claim to a global hardware-demand forecast. The two are connected, but they are not interchangeable. A model can use less memory for one part of inference while still requiring substantial memory for its weights, activations, communication between accelerators and the total throughput demanded by a production service.
The immediate market move therefore signals concern about near-term semiconductor demand. It does not, by itself, measure worldwide HBM consumption or establish a lasting change in the fundamentals of Samsung Electronics or SK Hynix.
The memory DeepSeek is actually optimizing
HBM is stacked DRAM positioned close to an accelerator so data can move at very high bandwidth. It is a central resource in demanding AI training and inference systems, but it is not the same thing as a model’s KV cache.
The KV cache stores key and value information generated by the attention mechanism as a model processes a conversation or other long sequence. Because that stored state grows with context length, it can become a major source of accelerator-memory pressure during inference.
DeepSeek’s Multi-Head Latent Attention (MLA) addresses that pressure by compressing key/value information into latent representations that can be cached. A smaller attention state can mean less memory is needed for that particular part of the workload.
Engram takes a different route. It describes conditional memory connected to an offloaded memory hierarchy, allowing some static or retrievable knowledge to sit outside the accelerator’s most constrained memory. The accelerator still performs the model’s active computation, while the memory system handles information that does not need to remain entirely on the device.
These mechanisms should not be collapsed into one headline number. MLA concerns compressed attention state. Engram concerns conditional memory and offloading. Neither is a declaration that all physical HBM requirements have vanished.
What the reported DeepSeek V4 figures mean
A secondary account attributed two figures to DeepSeek V4 at a one-million-token context: 10% of DeepSeek V3.2’s KV-cache requirement and 27% of its single-token inference FLOPs.
Those are specific workload metrics. The first describes KV-cache use relative to DeepSeek V3.2; the second describes computation for single-token inference. Neither is a measurement of total HBM capacity, HBM shipments or memory-chip revenue.
A separate technical chart shows DeepSeek V4-Pro with 13.7× lower accumulated KV cache than DeepSeek V3.2 at a 1,024K sequence length. That figure belongs to a different model label and presentation. It should not be merged with the 10% figure as though both measured the same variant, baseline or condition.
The practical lesson is simple: always ask which memory, which model, which workload and which context length? Without those four details, “less memory” is too vague to support a hardware-demand forecast.
Why KV-cache savings do not equal lower HBM shipments
Think of an AI accelerator as a busy workshop. The KV cache is one stack of parts beside the workbench—not the entire building. Making that stack smaller creates room, but it does not remove the machinery, raw materials or traffic moving through the facility.
Several other factors still matter:
- Model weights: the trained parameters must be stored somewhere accessible to the system.
- Activations: intermediate values are created as the model processes input and generates output.
- Attention and computation: compressing cached state does not eliminate the operations that produce the result.
- Communication: multi-accelerator systems still move data between devices and memory pools.
- Workload shape: long contexts, batch size, response speed and total concurrent users change the memory requirement.
Software optimization can also make constrained hardware more useful without changing its physical memory capacity. A comparison of NVIDIA H100 and H800 systems illustrates the distinction: the H100 is shown with 900 GB/s of interconnect bandwidth, while the H800 is shown with 400 GB/s. Techniques such as lower-precision computation and low-level tuning can help manage bandwidth bottlenecks, but they do not turn memory capacity into bandwidth—or make the two resources interchangeable.
HBM and DDR5 belong to different parts of the system as well. HBM is built for very high bandwidth near an accelerator; DDR5 is general-purpose system memory. One cannot simply replace the other in every AI workload.
Could more efficient AI increase memory demand?
Yes, at least in principle. If inference becomes cheaper, providers may run more requests, support longer contexts or make AI features available to more people. That possibility is often described through Jevons’ paradox: efficiency gains can increase total consumption when they make a resource cheaper to use.
This is a possibility, not a measured market result. The opposite outcome is also possible for workloads where lower memory pressure directly reduces the amount of hardware needed. The balance depends on deployment scale, model demand, service economics and the mix of training and inference workloads.
That is why the stock reaction should be read as an early market concern, not as a final verdict on HBM.
The reported market reaction in context
| Company or benchmark | Reported share movement on 11 September 2026 | Price-to-book context | Distance from all-time high |
| Samsung Electronics | −3.5% | 2.7× current book value | More than 25% below |
| SK Hynix | −2.2% | 5× current book value | More than 25% below |
| Philadelphia Semiconductor Index | — | 11× book value | — |
The valuation figures provide context for how the companies were being viewed at that moment; they are not a recommendation to buy or sell. Daily market prices move quickly, and a single session cannot settle a question about long-term semiconductor demand.
What the evidence supports—and what it does not
DeepSeek’s reported efficiency work can reduce KV-cache use and ease accelerator-memory pressure in particular inference conditions. Engram’s offloaded memory hierarchy can move some conditional-memory work away from the accelerator. MLA can compress the attention state retained during inference.
Those are meaningful engineering developments. They are not equivalent to a confirmed reduction in total HBM capacity, HBM shipments or worldwide demand. HBM remains relevant to model weights, activations, attention, communication and high-throughput deployment.
For now, the clearest conclusion is also the most useful one: DeepSeek may be making AI inference more memory-efficient, but the 11 September market reaction does not prove that HBM demand has permanently fallen. The next move will depend not only on memory saved per request, but also on how much that efficiency expands the number of AI requests the industry can afford to run.