SK hynix has described an SSD-controller design that assigns routine input/output (I/O) work to about 100 specialized H-TPU processors, while a general-purpose CPU handles complex management. The Elec reports that SK hynix vice president Koo In-je presented the architecture at ISOCC 2026. The Elec’s report expands H-TPU as Hynix Transaction Processing Unit: a processor for SSD transactions, not an AI tensor processor.
Routine I/O for H-TPUs, complex management for the CPU
The H-TPUs are designed to handle repetitive read and write processing, metadata management, and buffer control. The general-purpose CPU retains storage-policy management, error recovery, and exception handling. In other words, the design offloads routine tasks rather than replacing the CPU.
SK hynix described roughly 100 H-TPUs in a controller, with the units needed for a particular I/O request activated while the others can idle. That divides the work among specialized processors without assigning every controller responsibility to them.
A four-stage pipeline with dedicated development tools
Each H-TPU uses a four-stage pipeline and executes instructions sequentially, according to The Elec. The publication also reports that SK hynix developed a dedicated compiler and related tools to help engineers write code for the processors.
What the power and area figures compare
The Elec reports that SK hynix put each H-TPU’s power at 2.5% and its area at 4% of a general-purpose CPU core. Those are per-core comparisons: they describe the relative power and area of an H-TPU against one CPU core, not the power or area of an entire SSD controller.
Storage Next and other planned uses
SK hynix plans to apply the architecture to next-generation enterprise SSD controllers and other NAND products, with Storage Next and High-Bandwidth Flash (HBF) also among the reported future applications. The Elec describes Storage Next as targeting data accesses of 512 bytes or less, compared with conventional 4 KB access units.
