On October 19, 2026, Sohu reported that ZTE Microelectronics had publicly shown Zhufeng 200 at the 2026 RISC-V China Summit in Shenzhen, describing it as a RISC-V CPU for intelligent-computing centers. The report attributes three intended AI infrastructure roles to the processor: Agent CPU clusters, inference-supernode host CPUs, and enterprise hybrid inference (Sohu’s report). NeoTeo also covered the 2026 RISC-V China Summit.
The AI system roles Sohu described
Sohu attributes the three intended uses to Shi Yijun, ZTE Microelectronics’ wireless and computing business general manager. Agent CPU clusters would handle many lightweight, concurrent tasks and tool calls. In an inference supernode, the CPU would work alongside GPUs or other accelerator cards, supporting smaller large language model (LLM) inference and instruction-level key-value cache (KV Cache) optimization. For enterprise hybrid inference, it would pair with XPU accelerator cards and execute “cold” experts in a mixture-of-experts (MoE) model.
Architecture and interfaces in the presentation
Sohu’s account of the presentation describes a 64-bit, superscalar, out-of-order CPU design, with RISC-V RVA23, Hypervisor, AIA, CoVE, and RVV 1.0. It also lists Vector and Matrix compute, acceleration for retrieval-augmented generation (RAG) retrieval and reranking, and compression and encryption engines. The reported memory and I/O list includes DDR5, MRDIMM, PCIe 6.0, and CXL 3.
Sohu also relayed a claim that Zhufeng 200 could run MoE models at the hundreds-of-billions-of-parameters scale. It reported that the presentation did not disclose exact product parameters.
What the Sanechips product page lists
The official Sanechips ZhuFeng page lists the ZhuFeng family and links to ZhuFengXin specifications, but does not name Zhufeng 200.
Sohu forecast a formal product release by the end of 2026.
