CUDA on RISC-V uses a RISC-V CPU to host the operating system, drivers and applications; an NVIDIA GPU executes the CUDA kernels. NVIDIA disclosed its intention to bring CUDA to RISC-V in 2025, and SiFive later demonstrated an inference workflow on its BigSky SF-2U870 server. The reported host requirements point to a server-grade platform, not just any RISC-V board.
What “CUDA on RISC-V” means
CUDA is NVIDIA’s platform for running computing workloads on its GPUs. In this arrangement, RISC-V describes the host CPU’s instruction-set architecture: the CPU runs the system software, while the NVIDIA GPU does the parallel computation. The demonstration uses an NVIDIA GPU, not the RISC-V CPU as the CUDA accelerator.
Reported requirements for a RISC-V host
The reported requirements include the RVA23 profile, RISC-V server system-on-chip and platform specifications, firmware services, vector extensions with predication, and specific PCIe capabilities. Each addresses part of the system needed to connect the host software and GPU hardware.
| Requirement | Platform role | Practical effect |
| RVA23, plus RISC-V server SoC and server platform specifications | Establishes the reported instruction-set and system baseline | Gives software and hardware a defined server platform to target |
| ACPI and RISC-V Boot and Runtime Services (BRS) | Supports hardware discovery and firmware services; ACPI also covers power, performance and thermal management | Helps the operating system identify and manage platform hardware |
| Vector extensions with predication | Provides vector operations and ways to control which operations apply | Can help avoid branches in suitable code |
| PCIe I/O coherency | Keeps CPU and GPU memory views consistent during transfers such as direct memory access (DMA) | Reduces the risk of one device using stale data from the other’s cache |
| PCIe peer-to-peer (P2P) | Allows transfers directly between devices | Avoids routing those transfers through host memory |
PCIe coherency and peer-to-peer support address different parts of data movement. Coherency concerns whether devices see current memory values; P2P concerns the route data takes between devices.
What SiFive’s BigSky demonstration runs
SiFive’s BigSky SF-2U870 pairs a RISC-V host with NVIDIA GPUs. Its announced configuration includes 32 SiFive P870-D cores at 2.0 GHz, 256 GB of DDR5-5600 memory, four PCIe Gen5 x16 connections with 64 lanes total, PCIe Gen3 x4, two 7.68 TB U.2 NVMe SSDs, and a 10/25 Gb OCP 3.0 network interface. SiFive lists Ubuntu 26.04 LTS and Red Hat RHEL 10 as supported out of the box.
SiFive describes BigSky as a head node for large language model workloads on NVIDIA GPUs. In its September 25, 2026 demonstration, LLaMA.cpp runs with Gemma 4 in a CUDA inference workflow. Inference means using a trained model to generate outputs; it is a different workload from training a model.
SiFive said on August 24, 2026, that BigSky was available in limited quantities and that demand exceeded supply. That statement describes the company’s position on that date.
