Deep ultraviolet (DUV) multiple patterning builds a complex chip layer by printing several simpler patterns in successive exposures and aligning each with features already etched. Chinese chipmakers can use this approach to make advanced-class chips without extreme ultraviolet (EUV) lithography; the added alignment work and its effects on die size and yield shape the economics.
How multiple patterning works
A lithography system transfers patterns onto a silicon wafer, the thin disc from which chips are cut. With multiple patterning, a manufacturer divides a complex layer into simpler patterns, prints them in separate exposures, then aligns each new pattern with the structures already formed. Think of drawing a detailed image with transparent stencils: every layer must line up with the ones beneath it.
That alignment is called overlay. More exposures create more opportunities for overlay errors and process variation. To make a design easier to manufacture, chip designers may leave more space around features. That can enlarge each die, the individual chip cut from a wafer.
Why more exposures affect the economics
Chris Mack, co-founder and CTO of Fractilia, described a conventional cost comparison: three exposures using a 193-nanometer immersion DUV tool cost about as much as one EUV exposure. He said EUV became more cost-effective when four DUV masks would be replaced by one EUV mask.
| Patterning case | Reported cost comparison | Economic interpretation |
| Three 193-nanometer immersion DUV exposures | About the cost of one EUV exposure | Mack's conventional comparison puts the costs in roughly the same range. |
| Four DUV masks replaced by one EUV mask | Mack said EUV became more cost-effective | The relative economics shift as the number of DUV masks rises. |
The comparison is about exposure costs, not the total cost of a finished chip. Repeated patterning can also add process complexity. If designers leave more space between features, each die may take up more of the wafer. Larger dies mean fewer fit on a wafer, while manufacturing yield determines how many of those dies become saleable chips. Wafers can cost tens of thousands of dollars, so the number of good chips produced from each one matters.
What memory and logic examples show
Micron's 1-alpha DRAM generation used 193-nanometer lithography without EUV. Its 1-gamma DRAM process uses EUV, and Micron reports more than 30% greater bit density per wafer than its preceding 1-beta generation. DRAM stores data in repetitive structures that are easier to coordinate with manufacturing than the more complex patterns in logic chips. The memory example therefore describes DUV's reach in DRAM, rather than the economics of producing complex logic.
A reported analysis of Huawei's Kirin 9030 placed SMIC's process near density associated with 5-nanometer manufacturing, while finding it less scaled than leading 5-nanometer processes from Samsung and TSMC. Chris Mack has cautioned that process-node names alone say little about whether two manufacturing processes are equivalent. Density and a label such as “5nm” describe only part of the comparison.
