OpenAI’s Jalapeño is a custom accelerator for large language model (LLM) inference: running a trained model to generate responses. OpenAI says its models assisted selected design, optimization and verification tasks, while engineers remained responsible for decisions and Broadcom handled physical design. The work was AI-assisted, not an end-to-end automated chip design.
Where AI helped in Jalapeño’s design
OpenAI says its models helped engineers explore different implementations, shorten design, measurement and verification loops, and optimize arithmetic circuits. The assistance fit especially well in software-like front-end work: the early stages where engineers describe and refine what a chip should do.
That workflow used XLS, a high-level synthesis system. High-level synthesis turns a higher-level description of hardware into a design that can be implemented as circuitry. Because this work resembles software development, it offered a natural place for AI assistance. OpenAI engineer Chris Leary described the models as more useful for these software-like tasks.
That is a specific contribution, not a claim that a model independently created the chip. OpenAI hardware leader Richard Ho said engineers directed the work and made the final decisions. Models helped them explore and iterate; people remained in charge of the engineering.
How OpenAI, Broadcom and Celestica divided the work
OpenAI led the end-to-end system design, shaping the accelerator around the inference workloads it intended to serve. Broadcom contributed to silicon implementation and handled physical design—the work of turning the chip’s logical design into a practical physical layout. Celestica contributed to board, rack and system integration.
The distinction matters: designing a chip’s behavior is only part of building a functioning system. Physical design and the integration of boards and racks are separate engineering tasks, and the reported project involved specialists across those stages.
The OpenAI design group averaged fewer than 100 people, excluding Broadcom personnel, according to Richard Ho. That figure describes OpenAI’s group, not the total number of people involved across the partners.
What the reported timelines measure
The two headline durations describe different stretches of work. The reported nine-month interval ran from first RTL to tape-out. RTL, or register-transfer level, describes a chip’s digital logic and how data moves between its parts; tape-out is the point when a finalized design is sent for manufacturing.
A separate reported milestone puts the span from architecture concept to first silicon at under 20 months. The first figure ends at tape-out; the second reaches the first manufactured silicon and starts earlier, at the architecture concept. They measure different stages of Jalapeño’s development.
OpenAI and Broadcom announced Jalapeño on June 24, 2026, as an inference chip and the first part of a multi-generation compute platform.
