Huawei is reportedly unveiling the Ascend 960 SuperPoD at Huawei Connect 2026 in Shanghai on September 17, 2026, alongside a faster roadmap for two chip variants planned for 2027. The move puts Huawei’s strategy in plain view: compete with Nvidia not only through an individual accelerator, but through the full system that connects thousands of chips, memory and networking.
Huawei’s Ascend 960 SuperPoD was reportedly unveiled in Shanghai
The Ascend 960 is Huawei’s next-generation AI accelerator family and the successor to the Ascend 950 series. The Atlas 960 SuperPoD is the larger system built around those accelerators, designed to combine many computing nodes into one logical machine for demanding AI workloads.
Huawei says the system is intended to support training and inference for models with up to 10 trillion parameters. The reported unveiling also highlights near-packaged optics, an approach that places optical connectivity closer to the computing hardware to help move data through a large-scale system.
That distinction matters. Training a huge model is not just a matter of placing a faster chip on a circuit board. Thousands of accelerators must exchange data quickly and consistently; otherwise, the network becomes the traffic jam that ruins the party. Huawei’s pitch is therefore about the entire computing fabric: accelerators, memory, interconnects and software working as one platform.
Why the SuperPoD matters more than a faster chip alone
Huawei’s roadmap emphasizes system-level scaling through its SuperPoD architecture and UnifiedBus interconnect technology. The 2025 Atlas 960 target calls for up to 15,488 Ascend 960 chips, distributed across 220 cabinets—176 compute cabinets and 44 communications cabinets—in a deployment covering 2,200 square meters.
The same roadmap set targets of 30 EFLOPS FP8 and 60 EFLOPS FP4 for the complete Atlas 960 SuperPoD, plus 4,460 TB of memory and 34 PB/s of interconnect bandwidth. FP8 and FP4 refer to numerical formats used in AI computation; lower-bit formats can help process certain workloads more efficiently when the software and models support them.
At chip level, Huawei’s stated Ascend 960 targets are 2 PFLOPS FP8 and 4 PFLOPS FP4. Huawei also described the chip as doubling the Ascend 950 series’ computing power, memory-access bandwidth, memory capacity and interconnect-port count.
The architecture-first approach is Huawei’s answer to a difficult reality in AI infrastructure: a system’s usefulness depends on more than the peak number printed on one accelerator. Large model training also depends on how efficiently chips share data and how much memory the system can address as a whole.
The 960DT and 960PR roadmap moves forward
The 2025 general roadmap placed Ascend 960 availability in the fourth quarter of 2027. Later reporting separates the family into two workload-focused variants and places them earlier on the calendar:
| Subject | Role or scope | Target or schedule |
| Ascend 960 | Next-generation AI accelerator family | 2 PFLOPS FP8 and 4 PFLOPS FP4; Huawei roadmap target |
| Atlas 960 SuperPoD | Large-scale system built around Ascend 960 chips | Up to 15,488 chips; 30 EFLOPS FP8 and 60 EFLOPS FP4; Huawei roadmap target |
| Ascend 960DT | Training-oriented variant | Q1 2027, according to the reported rollout schedule |
| Ascend 960PR | Inference-oriented variant | Q3 2027, according to the reported rollout schedule |
The Ascend 960DT is expected to be ready for model-training use in the first quarter of 2027. The Ascend 960PR is scheduled for the third quarter of 2027 for inference workloads, meaning the stage in which a trained model generates answers or predictions.
Those dates describe the reported roadmap for the two variants. They do not turn a planned milestone into a completed rollout. Huawei has also described an annual generation cycle, with Ascend 970 planned for 2028 and Ascend 980 planned for 2029.
What Huawei’s earlier official roadmap actually specified
Huawei introduced the Ascend 950, 960 and 970 roadmap on September 18, 2025. That plan presented Ascend 960 as a major step in four areas: computing power, memory capacity, memory-access bandwidth and the number of interconnect ports.
The roadmap also included support for HiF4, Huawei’s proprietary 4-bit format. At the system level, Atlas 960 was presented as a much larger target than the preceding Atlas 950 SuperPoD: 30 EFLOPS FP8 and 60 EFLOPS FP4, compared with 8 EFLOPS FP8 and 16 EFLOPS FP4 for Atlas 950. Its interconnect target was 34 PB/s, compared with 16 PB/s for Atlas 950.
These are Huawei’s stated design and performance targets. They explain the scale of the planned platform, but they do not by themselves measure how an Ascend 960 system performs on the same workload, software stack and operating conditions as an Nvidia system.
The unanswered Nvidia question
Huawei’s executives and outside analysts have framed packaging, optical networking, rack-scale architecture and software-hardware co-optimization as ways to narrow the system-level gap with Nvidia. That is a different claim from proving that one Ascend 960 accelerator is faster than one Nvidia accelerator.
No independent same-condition benchmark establishes that Ascend 960 is faster than Nvidia hardware. For now, the meaningful development is Huawei’s attempt to make the complete AI system—rather than the standalone chip—the unit of competition, with the 960DT and 960PR roadmap supplying the next scheduled steps.
