A forum post dated September 25, 2026, described a rumored AMD RDNA 5 AT0 layout with one XCD, one AID and one MID. The proposal divides graphics compute, memory-related functions and display connectivity among three dies.
The revised AT0 chiplet proposal
The three-die arrangement differs from an earlier version of the rumor, which described seven dies: one MID, two AIDs and four SEDs. The revised proposal instead describes a single XCD—not several compute chiplets.
What each proposed die would do
The reported functional mapping gives each die a different job. A die is a separate piece of silicon within a chiplet-based processor package; the acronyms here identify the proposed roles, not confirmed AT0 specifications.
| Die | Proposed function |
| XCD | Graphics compute and shaders |
| AID | Memory controllers, physical-layer (PHY) interfaces and L2 cache |
| MID | Display engine and links, plus PCIe |
One proposed compute die
Under this layout, graphics compute would sit on one XCD rather than being split among multiple compute chiplets. The arrangement remains a rumor, not an AMD product announcement.
