Intel reports more than 1 million High-NA wafers—but stitching remains the hurdle

Intel reported in September 2026 that it had processed more than 1,000,000 300-mm wafers through High-NA EUV scanners. That is a striking utilization milestone, but it is not a claim that 1 million fully commercial wafers were each processed entirely with High-NA EUV: the cumulative total includes installation, certification, research and development, and production activity.

The more consequential story is what Intel is trying to solve next. High-NA EUV can print smaller features with fewer patterning steps, but its anamorphic optics reduce the exposure field available with today’s conventional masks. For large dies, that can mean stitching two exposures together—and accepting a throughput and alignment penalty.

What Intel’s million-wafer figure actually counts

The reported total covers 300-mm wafers processed across several stages of Intel’s High-NA program. It includes work used to install and certify the equipment, research and development activity, and production activity. The figure therefore measures accumulated use of the scanners, not a clean count of finished commercial wafers.

That distinction matters. Repeated processing gives a manufacturer valuable experience with equipment setup, process integration, optimization, maintenance, and defect control. It can create a meaningful learning advantage. But wafer volume alone does not reveal the resulting yield, cost per wafer, power characteristics, transistor density, customer volume, or production scale.

Intel had previously been reported to have processed approximately 30,000 High-NA wafers by late February 2025. The later million-wafer milestone represents a much larger period of accumulated activity.

Intel’s High-NA work is built around ASML’s TWINSCAN EXE platform. High-NA uses a numerical aperture of 0.55, compared with 0.33 for conventional EUV. Numerical aperture describes how much light a lithography system can collect and at what angles; a higher value can support finer printed features, but it also changes the geometry of the exposure system.

ASML describes the EXE platform as supporting 8 nm resolution and 40% higher imaging contrast than NXE. Those are manufacturer-stated platform figures, not independent measurements of Intel’s production results.

The High-NA field-size problem

The catch is the mask—or reticle—that carries the pattern to be printed. High-NA’s anamorphic optics use different magnification in the two axes: 4×/8× rather than the conventional EUV system’s 4×/4× arrangement.

With a standard 6×6-inch mask, the reported High-NA exposure field is approximately 26×16.5 mm. Conventional 0.33-NA EUV can expose a field of approximately 26×33 mm with a standard mask. In simple terms, High-NA offers finer imaging, but the usable field is half as tall in one direction.

That difference becomes important when a chip die is too large for one High-NA exposure. A manufacturer can redesign the die around the smaller field, or it can expose the design in two sections and join them precisely. The second approach is called stitching.

Stitching trades coverage for throughput and alignment

Stitching uses two successive High-NA exposures to cover a larger die. The boundary between those exposures must line up accurately enough that the circuit pattern behaves as one continuous design. Any alignment error at the seam can create manufacturing problems, making overlay control and process stability especially important.

The trade-off is not merely theoretical. For the EXE:5200B, reported throughput falls from 175 wafers per hour without the stitching penalty to 125 wafers per hour when stitching is used. Those figures describe a reported throughput comparison under the two exposure conditions; they are not a universal production rate for every chip or factory.

This is why the mask format is central to the story. The machine may offer finer imaging, but the factory still has to balance field coverage, exposure count, alignment, cycle time, and yield.

Why Intel wants a 6×12-inch mask

Intel is working with industry partners on 6×12-inch photomasks intended to restore a complete 26×33 mm High-NA field in one operation. In principle, that would remove the need to stitch two exposures for dies that fit within the larger field.

The intended benefit is clear: fewer exposure steps could simplify layout planning and avoid the throughput penalty associated with stitching. It could also reduce the number of alignment-sensitive boundaries inside a large die. Those are manufacturing objectives, not evidence that the larger-mask approach has already been deployed.

The development still faces practical questions. Compatibility of current or planned scanners with 6×12-inch masks, and whether the larger-mask ecosystem will become an industry standard, remain open engineering questions. Mask manufacturing, handling, inspection, tooling, and scanner design would all have to work together at the required precision.

The proposal is therefore best understood as an engineering direction: Intel is trying to preserve High-NA’s imaging advantages without accepting the smaller field as an unavoidable limit for large designs.

Intel and TSMC are making different timing bets

Intel’s reported activity puts it far earlier in High-NA utilization than the reported TSMC plan. TSMC is reported to be targeting High-NA EUV adoption around 2030 for advanced-node high-volume manufacturing. That remains a future plan, not completed adoption.

Tool maturity, cost, and the number of scanners required in an advanced fab are important considerations. High-NA equipment is expensive and integrating it into a high-volume factory involves more than installing a scanner: the surrounding process, masks, metrology, maintenance, and production economics all matter.

The comparison shows different timing choices, not a complete ranking of manufacturing technology. Intel’s cumulative wafer count is a strong measure of High-NA use. It is not a substitute for comparable yield, cost, power, density, customer, or production-volume data from Intel, TSMC, and Samsung.

What the milestone proves—and what it does not

The defensible conclusion is narrower than the loudest interpretation. Intel’s reported total supports a substantial High-NA utilization and process-learning lead. More experience with a new lithography platform can help a manufacturer learn how to integrate it into production and optimize the surrounding process.

But the milestone does not by itself prove that Intel has better overall process technology than TSMC or Samsung. It does not establish superior yields, lower costs, better power efficiency, higher transistor density, greater customer adoption, or a two- to four-year lead across the semiconductor business. Those questions require like-for-like measurements that are not part of the reported wafer total.

It also does not turn Intel’s 6×12-inch mask effort into a finished capability. The proposal is aimed at solving a real High-NA limitation, but its manufacturing status, scanner compatibility, and eventual industry role remain future-facing.

For now, Intel has demonstrated the most important thing a new lithography platform needs before it becomes routine: sustained use at scale. The next test is whether that experience can translate into efficient production—especially when the choice is between accepting stitched exposures or changing the mask ecosystem itself.