Micron presented its Edge Inference Memory (EIM) development direction at SEDEX 2026 in Seoul, held the week before October 20, according to BusinessKorea. The same October 20 report covered ChangXin Memory Technologies (CXMT)’s reported DRAM progress. Together, the developments point to different memory approaches and milestones across the industry.
How EIM differs from PIM
BusinessKorea describes EIM as low-power DRAM, or LPDDR, stacked on a logic die that handles AI computation. The design aims to reduce latency between an AI chip and memory while increasing bandwidth. Micron was also reported to be discussing physical-AI products with major customers for autonomous driving, humanoid robots, augmented reality and virtual reality.
Processing-in-memory (PIM) places computing units inside memory. In the reported EIM arrangement, LPDDR sits above a separate logic die. The two terms therefore describe different placements of the computing logic.
BusinessKorea characterized mass production in the second half of 2028 as an industry expectation for EIM. Micron presented its development direction at SEDEX; the reported 2028 timing was an industry expectation.
CXMT’s reported DRAM milestones
BusinessKorea reported that CXMT said it had introduced self-aligned quadruple patterning (SAQP) and made progress on a 4F² DRAM architecture. The report also said CXMT announced LPDDR6 mass production in August 2026 and entered mass production on its fifth-generation DRAM process in September 2026.
CXMT planned to introduce next-generation server products using the architecture by the end of 2026. That is a planned product introduction, distinct from the reported mass-production milestones for LPDDR6 and the fifth-generation process.
Samsung’s reported 4F² development stage
On October 15, 2026, DIGITIMES reported that Samsung Electronics had reportedly completed development of 4F² DRAM and was aligning commercialization with customer requirements. That account describes a development stage; CXMT’s reported plan concerns the introduction of next-generation server products. The reports describe separate steps in memory development, rather than a shared performance result.
