A report published October 2, 2026, says OpenAI is deploying its Jalapeño inference ASIC internally alongside AMD EPYC Turin host CPUs. OpenAI hardware chief Richard Ho said the Turin platform offered a mature, lower-risk path for moving quickly on the design.
What EPYC Turin does in the Jalapeño system
Jalapeño is an application-specific integrated circuit, or ASIC, designed for AI inference: the computing work involved in running a trained model. AMD EPYC Turin processors serve as host CPUs paired with the Jalapeño accelerators.
The described configuration has two Turin-class EPYC CPUs and 1.5TB of DRAM in each host. Its rack layout pairs 16 host trays with 16 Jalapeño trays, each holding eight ASICs—128 Jalapeño chips per described rack. Each host tray connects to its corresponding accelerator tray through eight external PCIe direct-attach copper (DAC) cables; PCIe Gen 5 provides system I/O to the x86 host CPU.
Why OpenAI chose Turin over Nvidia Vera
Richard Ho, OpenAI’s vice president and head of hardware, said the team chose Turin for its maturity and because partners already had experience with the platform. He described the decision as a way to move quickly while avoiding unnecessary design risk. At the time, Ho considered Nvidia Vera less mature as a standalone option.
The reported deployment and the 2027 production schedule
A report published August 25, 2026, described Jalapeño engineering samples and a gradual production ramp scheduled for 2027, with most output planned for the end of that year. The later report of internal deployment describes a separate stage of the rollout.
OpenAI’s own compute demand comes first
Ho said OpenAI expected to prioritize its own compute needs for a long time, while leaving open the possibility of use by others. He announced no outside sales. That internal-use priority also featured in NeoTeo’s earlier coverage of Jalapeño.
