RISC-V’s 2026 processor forecast puts server requirements in focus

At the sixth RISC-V China Summit, held in Shenzhen October 18–20, RISC-V International CEO Andrea Gallo forecast that high-performance RVA-based RISC-V application processors would arrive in 2026, according to EET China's October 20 account. For data-center use, a processor core is only one part of the platform: RISC-V International's server requirements cover interrupt delivery, DMA protection, PCIe, reliability, management and security. The summit followed the schedule in NeoTeo's earlier event preview.

What the server SoC requirements cover

The RISC-V Server SoC Requirements v1.0 specifies system-level rules and recommendations for server-on-chip platforms. It covers timers, interrupts, IOMMUs, PCIe, reliability, availability and serviceability (RAS), quality of service (QoS), management, performance monitoring and security.

The distinction between “MUST” and “SHOULD” matters. A MUST clause is a requirement; a SHOULD clause is a recommendation. For example, the specification requires a hardware root of trust as the primary root of trust. It recommends support for encryption of off-chip DRAM and an interface for a Trusted Platform Module (TPM) 2.0.

These rules describe a platform, not a certification or performance result for any particular processor. A core count or an ISA profile alone cannot establish that a complete server system meets them.

Interrupts and device memory access

The specification requires support for the RISC-V Advanced Interrupt Architecture (AIA), with external interrupts delivered as message-signaled interrupts (MSIs). An incoming message-signaled interrupt controller (IMSIC) must provide an S-mode interrupt file and at least five VS-mode interrupt files. Those VS-mode files let a hart maintain interrupt contexts for multiple virtual CPUs without swapping each file's contents to memory.

An IOMMU, or input-output memory management unit, controls how devices access memory through direct memory access (DMA). The requirements place DMA-capable peripherals and software-accessible PCIe root ports under IOMMU control, subject to listed exemptions. That lets operating systems and hypervisors restrict device access to permitted memory, including when assigning devices to virtual machines.

PCIe, reliability and security

PCIe connects the processor platform to devices such as network adapters and accelerators. The requirements cover root ports, the host bridge and the handling of device errors, among other functions. RAS provisions address error reporting and recovery; QoS recommendations describe ways to reduce interference when workloads share resources such as memory bandwidth and cache capacity.

The specification also recommends standardized server-management protocols. Those can support monitoring and control through a baseboard management controller, including access to sensor readings and error logs. Together, these requirements make server readiness a system-level question involving hardware and software, rather than a property of the instruction set alone.

What the summit account says about individual platforms

EET China described SiFive BigSky as a data-center development platform with 32 RVA23 cores running at 2.0 GHz and Ubuntu 26.04 LTS. The same account described Epic Semi's Contrail AIX as commercialized, with 32 scalar cores, 16 AI accelerator cores and a reported 75 TOPS. Those configurations and statuses are reported claims, not comparable performance measurements or evidence of compliance with the server requirements.

EET China also reported that Tenstorrent's Atlantis platform uses an eight-core Ascalon X cluster. SoC and board power-on was planned for Q4 2026. That is a development milestone, distinct from a performance result or a statement of market availability.

RISC is not a speed rating

RISC describes a processor-design approach that commonly uses simple, regular instructions, with separate load and store operations for memory and register-based arithmetic. CISC designs have traditionally allowed more complex instructions and memory operations. These are design tendencies, not a ranking of processors: the performance of a particular chip depends on its implementation, software and workload.