SpacemiT’s V100 combines 46 RISC-V cores across two designs, and its published specifications spell out the memory capacity, PCIe lane arrangements and package dimensions that matter for planning a server platform. The company introduced the processor at RISC-V Summit China on October 20, 2026, alongside three server platforms. NeoTeo’s launch coverage covers that announcement; the V100 technical documentation provides the component-level details.
Two core designs in one processor
SpacemiT specifies six Kunminghu V2R2 cores and 40 X100 cores in the V100. The two designs have different maximum clocks and L2 cache sizes, while each has the same L1 cache capacity.
| Core design | Count in V100 | Manufacturer-listed maximum clock | Manufacturer-listed L2 cache | L1 instruction and data caches |
| Kunminghu V2R2 | 6 | 2.1 GHz | 1 MB | 64 KB each |
| X100 | 40 | 2.4 GHz | 2 MB | 64 KB each |
The processor also has 64 MB of shared last-level cache, or SLC. SpacemiT lists SPECint2006 figures of at least 15.0 per GHz per Kunminghu V2R2 core and 9.0 per GHz per X100 core. Those are manufacturer-published per-core figures, not independent benchmark results for the full processor.
Memory capacity and ECC
The V100 supports eight DDR5 channels with DDR5 RDIMMs at one DIMM per channel (1DPC). SpacemiT lists speeds up to 4,800 MT/s and peak memory bandwidth of 307 GB/s. Its stated capacity ceiling is 256 GB per DIMM and 2 TB per chip.
The specification also lists 80-bit ECC DIMMs per channel with sideband ECC. ECC, or error-correcting code, detects and corrects certain memory errors. The RDIMM requirement is a practical platform constraint: a design built around other DIMM types cannot be assumed compatible from these specifications.
How the 52 PCIe 5.0 lanes are grouped
SpacemiT specifies 52 PCIe 5.0 lanes. Its documentation describes three groups, each configurable as x16, x8x8 or x8x4x4, plus a separate x2x1x1 group. These arrangements describe lane allocation options for platform design; the lane total alone does not establish how a particular server board routes its slots or devices.
TDP, operating range and package size
SpacemiT lists a 120 W thermal design power (TDP), an operating-temperature range of 0–40 °C and an FCBGA package measuring 58.5 × 75.4 mm, with a 0.94 mm pitch. TDP is a processor specification, not a measurement of a complete server’s power draw. The temperature range and package dimensions are relevant to thermal and board design, but do not provide a whole-system consumption figure.
The server platforms announced with the V100
SpacemiT named three platforms with different intended roles: C2201 for general-purpose computing, G5201 for AI acceleration and S5236 for storage. The company says the G5201 supports eight full-height, full-length, double-width accelerator cards and RDMA, a way for systems to transfer data between memories with less CPU involvement.
SpacemiT also lists Linux kernel 6.6 and later, KVM and QEMU among the V100’s software support. Those entries add useful platform context, while the core, memory and interface specifications remain manufacturer-published figures rather than independent measurements.
