Infineon announced AURIX RC1 on November 4, 2026, as its first automotive microcontroller platform based on RISC-V. Separately, a report of an interview with Infineon executive Thomas Boehm attributes the platform’s processor IP to MIPS. Infineon’s announcement names RISC-V as the platform’s architecture.
RISC-V describes the instruction set; the MIPS connection is a reported attribution about processor IP.
What Infineon announced
Infineon positions AURIX RC1 as a common computing foundation for vehicle systems. The company targeted samples for the first half of 2027. Our earlier AURIX RC1 coverage looks at the platform’s broader automotive role.
How MIPS enters the account
A separate report attributes the identification of MIPS as the processor-IP supplier to an interview with Thomas Boehm. The interview page names Boehm as the interviewee and is dated November 4, 2026. That is the page’s publication date. The interview page
RISC-V and processor IP describe different layers
RISC-V is an instruction-set architecture: it defines the instructions a processor can execute. Processor IP is a reusable processor design that can be licensed and integrated into a chip. In this account, RISC-V is the architecture Infineon announced for AURIX RC1, while MIPS is the supplier named in the reported processor-IP attribution.
