On October 12, 2026, Cisco and NVIDIA announced plans for USFP, a pluggable optical-module design for AI data-center networks. Its first planned transceivers use 16 full-duplex lanes at 400 Gb/s per lane: 6.4 Tb/s in each direction, or 12.8 Tb/s summed across transmit and receive. Cisco’s announcement describes the design as a way to add network capacity while keeping a serviceable, pluggable approach.
Why AI networks need more optical capacity
AI data centers need to move large amounts of data among computing systems. Cisco says its proposed design is intended to support more bandwidth per connection and more connections per switch, while avoiding additional network tiers for more 1.6 Tb/s endpoints. Those are design goals, not results from a deployed network.
In a Bloomberg Tech interview published October 12, Cisco executive Jeetu Patel said increasingly powerful AI agents could use far more network bandwidth than people performing the same tasks. That workload context helps explain the interest in faster links; it is separate from USFP’s technical specifications.
What the 12.8 Tb/s figure counts
The proposed 16-lane configuration reaches 6.4 Tb/s in each direction: 16 × 400 Gb/s. The 12.8 Tb/s figure adds simultaneous transmission and reception, so it describes aggregate bidirectional capacity rather than throughput in one direction. Cisco’s announcement specifies the planned lane rate and configuration.
| Measure | Announced or calculated figure | Meaning |
| Initial lane configuration | 16 full-duplex lanes | Planned first transceivers |
| Rate per lane | 400 Gb/s | Announced electrical signal rate |
| Capacity per direction | 6.4 Tb/s | 16 lanes × 400 Gb/s |
| Bidirectional aggregate | 12.8 Tb/s | Sum of transmit and receive capacity |
| Bandwidth density | 4× | Cisco and NVIDIA’s comparison with 200 Gb/s-per-lane pluggable modules |
| Power efficiency | Approximately 1.3× | Cisco and NVIDIA’s comparison with 200 Gb/s-per-lane pluggable modules |
| Power dissipation support | Up to 100 W | Supported without a separate dedicated embedded cooling circuit inside the transceiver |
Cisco and NVIDIA also say the proposed design reaches four times the bandwidth density and about 1.3 times the power efficiency of pluggable modules rated at 200 Gb/s per lane. Those are company comparisons. The 100 W figure refers to supported power dissipation, a thermal-design measure, not an operating-power rating. Cisco’s announcement
Connector design and intended equipment
Cisco describes a two-dimensional array connector with two-step insertion. The company says the design aims to reduce contact wear, improve signal integrity and make insertion force more predictable. The planned transceivers are intended for switches and SuperNICs, and the first design uses an OSFP-sized footprint. Cisco also describes optical configurations intended to reduce latency and power through simpler signal processing.
The connector and optical features are design objectives; the announcement does not report measured performance for them. It also points to a future direction of 32 full-duplex lanes or more, distinct from the planned initial 16-lane configuration.
Partners and development stage
Cisco and NVIDIA are working with TE Connectivity and Amphenol on USFP cages, connectors and modules. They expect additional partners and plan to develop an open industry specification through a future community-led, multi-source effort. Cisco’s announcement
In an interview published October 13, Cisco SVP of Engineering Will Eatherton said the module had been simulated and tested and was ready to move to its next stage of development, as reported by FierceWireless. The Open Compute Project lists its 2026 Global Summit in San Jose, California, from October 12 through 15.
