Micron CTO Scott DeBoer said at the company’s October 21, 2026, Technology and Product Leadership webinar that Micron would not pursue commercial 4F² DRAM. He cited cost, complexity and scaling concerns, saying capacitor spacing matters more to practical memory density than the cell’s nominal area.
Why Micron is passing on 4F²
The comments came in response to UBS analyst Tim Arcuri’s question about why Micron saw no viable path for 4F² while competitors were investigating the design. Micron said the architecture could be built at older technology nodes, but with greater cost and complexity. DeBoer also cited scaling problems at the leading edge.
What the 4F² area advantage means
The 4F² and 6F² labels describe nominal memory-cell area. At identical feature dimensions, a 4F² cell has one-third less nominal area than a 6F² cell. A technical explanation by Tom’s Hardware calculates that this geometry could theoretically fit 50% more cells into the same area. That is an idealized cell-count comparison, not a measurement of a finished DRAM array.
The difference matters because cell area is only one part of array density. Capacitor size and pitch, the spacing between capacitors, constrain how closely cells can be placed. DeBoer said capacitor pitch is the key determinant of DRAM density, which is why Micron does not consider the smaller nominal cell area a sufficient commercial advantage.
Micron’s reported 3D DRAM path
DeBoer described 3D DRAM as a path between Micron’s 1-zeta and 1-eta nodes, with implementation timing dependent on economics. The decision to avoid commercial 4F² DRAM is a technology-roadmap choice; by itself, it does not signal additional DRAM production or a near-term price change.
NeoTeo has also covered HBM’s pressure on Chinese AI accelerators, a separate part of the region’s memory-industry story.
