ChangXin Memory Technologies (CXMT) said on September 20, 2026, that its fifth-generation G5 DRAM platform had entered mass production. The company presented two G5-based LPDDR5X products, each with 24 gigabits of capacity, as it pushes further into the low-power memory market for smartphones and portable electronics.
The announcement puts CXMT's latest manufacturing claims in the spotlight, but the practical story is more specific than a simple challenge to Samsung Electronics, SK hynix, or Micron Technology: G5 brings a reported process threshold, a new patterning approach, and a higher gross die count per wafer. Those figures describe the platform's claimed manufacturing characteristics, not a like-for-like commercial ranking.
What CXMT announced on September 20
CXMT said its G5 platform had reached mass production and displayed two LPDDR5X products built on it. Each product has a capacity of 24 gigabits, and the pair is available in two package formats intended for different smartphone and portable-device designs.
LPDDR5X is a low-power form of DRAM used where manufacturers need memory performance without the power demands of conventional desktop or server memory. In this case, the products are components for device makers rather than retail memory modules for consumers.
What CXMT showed in its G5 products
CXMT's LPDDR5X package carries the company's branding and shows both the package face and its underside, including the dense grid of contact pads used to connect the component. The render identifies the product family discussed here; the manufacturing figures come from CXMT's G5 announcement.
| Reported aspect | CXMT G5 detail |
| Platform | Fifth-generation G5 DRAM technology platform |
| Memory type | LPDDR5X low-power DRAM |
| Products presented | Two products |
| Capacity | 24 gigabits per product |
| Package formats | Two formats for different smartphone and portable-device designs |
| Storage-cell threshold | 11.95 nanometers |
| Patterning approach | Quadruple patterning, also described as quadruple exposure |
| Gross dies per wafer | At least 50% more than CXMT's fourth-generation platform, using an 8-gigabit reference chip |
What the 11.95-nanometer figure describes
CXMT reported an 11.95-nanometer threshold for relevant storage-cell structures in G5. That is a measurement tied to the platform's storage-cell design; it is not a universal process-node label or a direct equivalent to every competing DRAM manufacturer's published figure.
The reported process uses quadruple patterning, also called quadruple exposure in the announcement's coverage. In practical terms, the approach divides the creation of a fine pattern into multiple exposures rather than treating the number as a finished-chip performance score. CXMT presents the combination as part of G5's effort to improve density, energy efficiency, cost control, and the number of dies that can be produced from a wafer.
Why 50% more dies per wafer is not a yield figure
CXMT reported at least 50% more gross dies per wafer than its fourth-generation platform, with the comparison based on an 8-gigabit reference chip. Gross dies are the potential chip positions created on the wafer before defective units are removed. Final tested yield measures the share that passes testing, so the two figures describe different stages of manufacturing.
That distinction matters. A larger gross count can point to a denser or more efficient wafer layout, while the commercial result also depends on how many finished dies pass testing and what it costs to produce them. The G5 announcement supplies the first figure, not a final yield rate.
Where G5 fits in CXMT's LPDDR5X push
G5 follows an earlier CXMT LPDDR5X announcement with a different product set and status. CXMT said its 8,533 Mbps and 9,600 Mbps LPDDR5X products entered mass production in May 2025. In October 2025, the company said its 10,667 Mbps variant was available for customer sampling.
Those earlier speeds should be kept separate from the new G5 products: the September 2026 announcement identifies the two newer products by their 24-gigabit capacity and package formats, not by those earlier data-rate labels.
CXMT vice president and marketing-center head Luo Xiaodong described the company's process capability as comparable with the industry's most advanced mass-produced nodes. That is CXMT's process-positioning claim. It does not supply a like-for-like cost or yield benchmark against Samsung Electronics, SK hynix, or Micron Technology.
The move is part of CXMT's broader effort to build China's domestic memory capability as export controls restrict access to some advanced semiconductor manufacturing equipment and related software. For buyers and phone makers, the immediate news is the reported start of G5 mass production and the arrival of two higher-capacity LPDDR5X products; the broader competitive impact will depend on how the platform performs in commercial production.
