CXMT plans to launch a data-center server chip built around a 4F² DRAM design before the end of 2026, Bloomberg reported on October 13, 2026. At an industry conference in Shanghai over the preceding weekend, CXMT president Cao Kanyu described the plan; a company spokesperson confirmed his comments to Bloomberg.
TradingKey identifies the planned first application as DDR5 registered DIMM (RDIMM) server memory and describes the product as pre-launch. Its report places the announcement in conventional server DRAM.
What changes from 6F² to 4F²?
TradingKey compares conventional 6F² DRAM cells with CXMT’s claimed 4F² layout. On those nominal cell-area values, (6−4)/6 gives a 33.3% reduction. TradingKey says a smaller layout could theoretically increase storage density per wafer and lower cost per unit of capacity.
That is the architectural idea behind the announcement: smaller nominal cell area. Seoul Economic TV’s Korean-language report also explains the reported shift and discusses production hurdles.
What stands between the plan and a server product?
TradingKey identifies manufacturing yield, module testing, reliability, stable supply and qualification by server customers as steps toward a commercially established product. Each concerns a different part of the path from a cell design to memory modules that can be produced and supplied at scale.
Where the planned memory fits
The proposed DDR5 RDIMM is conventional server DRAM; high-bandwidth memory (HBM) is a separate memory category. TradingKey describes Kioxia primarily as a NAND-flash and SSD supplier, a different product category from CXMT’s planned DRAM. For the HBM angle in Chinese AI accelerators, see NeoTeo’s earlier coverage.
