MIPS announced Acies, Actus and Aegis on September 2, 2026, as RISC-V developer platforms for Physical AI. Acies targets edge inference, Actus real-time event processing, and Aegis safety-focused systems. MIPS lists Acies-1 at 50 TOPS and 10 W, while describing its performance and power figures as internal estimates or projections that vary with workload and implementation.
Three platforms, three workload roles
MIPS assigns each platform a different job: Acies is for AI inference at the edge, Actus for event-driven real-time computing, and Aegis for safety-focused applications. Physical AI here means AI computing used in systems such as vehicles, robots and industrial equipment.
| Platform | Stated focus | Intended workload |
| Acies | Inference-native edge AI | Running AI inference near the machines and devices using it |
| Actus | Event-native real-time embedded computing | Responding to events in motion control, sensor fusion and predictive maintenance |
| Aegis | Safety-native computing | Mission-critical Physical AI |
The roles address different constraints. Acies is centered on running models; Actus on timely responses to events; Aegis on safety-oriented systems. In an October 26 interview, MIPS described Actus-1 as based on Atlas M8500, with real-time multithreading, field-oriented-control acceleration and an ARC VPX 512-bit vector coprocessor. The interview described Aegis-1 as supporting RISC-V Android and Linux development and targeting ISO 26262 and ISO 21434 requirements.
What MIPS lists for Acies-1
MIPS identifies Acies-1 as an M.2 PCIe platform based on Atlas S8200. Its product page lists eight cores, more than 50 GB/s of memory bandwidth, and 50 TOPS at 10 W. MIPS says those performance and power figures are internal estimates or projections, may change, and depend on factors including the model, dataset, precision, optimization, memory behavior, power limits and system implementation.
The same page lists RVA23, RVV and VME support. For software, MIPS names Llama.cpp, Qwen, vision transformers and vision-language-action models as intended workloads. Its listed development tools include the Atlas SDK, Graph Performance Simulator and an IREE-based MLIR toolchain for ONNX, PyTorch and TensorFlow models.
An October 26 interview also attributed to MIPS a claim that S8200 offers more than 4× TOPS/W compared with current offerings. That is a company comparison, not an independent benchmark; it names neither a comparison product nor test conditions.
How RISC-V fits MIPS’s approach
RISC-V is an open instruction set architecture (ISA), the software-visible rules that define the instructions a processor can execute. It is a standard, not a particular chip. MIPS’s Acies page identifies Acies-1 as RISC-V-based, while an October 26 interview account dates MIPS’s shift from its proprietary namesake instruction set to RISC-V to 2021. For more on how RISC-V cores and AI accelerators work together, see NeoTeo’s RISC-V explainer.
MIPS’s platform strategy also includes software development before physical silicon is available. In the October interview, MIPS described Atlas Explorer as a virtual platform for running software and evaluating workloads before silicon. The same interview put the first S8200 silicon reference-platform samples on a 2027 timeline, as an expectation.
