PieceMakers pitches hybrid-bonded DRAM for edge AI after Taiwan debut

PieceMakers began trading on Taiwan’s Emerging Stock Board on September 16, 2026, at a NT$740 reference price while advancing a future-facing plan for edge-AI memory. The Taiwan-based company wants to place DRAM directly on a processor or logic wafer through hybrid bonding, putting its design between SRAM-heavy inference systems and conventional GPU packages built around HBM.

The idea is straightforward: reduce the distance that data has to travel. The business challenge is much less forgiving. Stacking more layers can improve capacity and bandwidth, but every additional layer puts more pressure on manufacturing yield.

What PieceMakers is trying to build

PieceMakers was founded in January 2006 and is headquartered in Hsinchu, Taiwan. Its business covers custom memory design, intellectual-property licensing, royalties, turnkey production and standard DRAM products, rather than commodity memory alone.

Its newer edge-AI strategy uses 3D stacking and hybrid bonding. Instead of keeping the memory separate from the processor in a conventional 2.5D package, the proposed design places DRAM directly on the processor or logic wafer. That shorter connection path is intended to support higher bandwidth, lower latency and less power spent moving data.

The approach is aimed at inference—the stage where an AI model produces an answer—rather than at the peak-throughput demands of large-scale model training. Edge systems also have tighter limits on power, physical area, price and memory capacity, so a design does not need to win every benchmark to be useful. It needs to balance several constraints at once.

PieceMakers says its manufacturing model would rely on the customer’s logic-wafer foundry for TSV and hybrid-bonding processes. That makes cooperation with the processor manufacturer part of the design challenge, not a detail that can be bolted on later.

The memory products behind the strategy

The company’s existing HBLL-RAM is a separate 2D, single-die product that can be integrated into a 2D system-in-package design without 2.5D or 3D technology. Its product page lists:

• 144 GB/s per die of random-access bandwidth;
• random-access latency below 20 ns;
• a 1 GHz clock;
• 2 Gb/s per pin;
• eight channels and 32 banks per channel; and
• energy consumption of 5 pJ/b.

The listed part is PLHP11440AK4, a 2.25 Gb device with a 288-bit interface. Those specifications belong to HBLL-RAM and should not be mixed with the company’s newer stacked architectures.

PieceMakers describes HiBaLL as a 3D-stacked product exceeding 1 TB/s. The newer wafer-on-wafer concept is reported at more than 2 TB/s per layer with latency below 20 ns. These are different architecture-level claims, while HBLL-RAM’s 144 GB/s figure is a per-die product specification.

A middle ground between SRAM and HBM

SRAM can deliver enormous bandwidth because it sits close to, or directly on, the processor, but its density is limited and the memory consumes valuable silicon area. HBM provides much more capacity and bandwidth in AI accelerators, but it depends on advanced packaging and keeps the memory in a separate stack connected to the processor package.

PieceMakers is targeting the space between those two choices: more capacity than an SRAM-heavy design, with a shorter and denser connection than a conventional off-chip memory arrangement. DRAM is not as fast as SRAM in every respect, but it offers a more practical density for edge systems that cannot devote large portions of the processor to memory.

That positioning also explains why PieceMakers is not presenting itself as a conventional HBM supplier. Its pitch is custom memory built around a particular processor or AI system, with the memory architecture and packaging designed together.

The company’s AI custom-design work accounted for almost 40% of its revenue in the first half of 2026, compared with approximately 4% in 2024. Nanya Technology owns a reported 33.96% of PieceMakers. Separately, Nanya Technology and Etron Technology announced an NT$500 million AI-memory design-services venture on August 7, 2025, with an 80/20 ownership allocation.

Why manufacturing yield is the hard part

Wafer-on-wafer memory increases the number of interfaces and process steps that must work together. A defective layer can affect the finished stack, so yield compounds as more layers are added.

Using the illustrative 80% yield per layer cited for the concept, four independent layers produce approximately 0.8⁴ = 41% aggregate yield. Eight layers produce approximately 0.8⁸ = 17%. That is not a production result from PieceMakers; it is a simple model showing why repair architecture and testing matter before bonding, after bonding and after logic integration.

The payoff for accepting that complexity would be a closer memory path and the possibility of combining DRAM density with a much wider interface. The cost is greater integration risk, tighter coordination with the logic foundry and potentially lower output from each wafer run.

When could it become a business?

The first volume customer program is expected to begin contributing financially in 2027 at the earliest. A possible ramp has also been described across 2027 and 2028, but the company’s commercial opportunity remains tied to customer co-design, foundry integration and the ability to produce stacked parts with acceptable yield.

For now, PieceMakers’ Taiwan market debut gives the strategy a public-company backdrop. The more important test will come when the proposed wafer-on-wafer architecture moves from a design and packaging proposition to sustained volume production.