TSMC plans A14 production for 2028; reported SRAM goal could mean over 19% less bit-cell area

Wccftech reported on October 29, citing DigiTimes, that TSMC’s A14 process was targeted for mass production in the first half of 2028. TSMC’s own plan sets production for 2028. Separately, a reported A14 SRAM bit-cell target below 0.017 μm² would mean more than roughly 19% less bit-cell area than TSMC’s 0.021 μm² 2nm reference, if achieved.

TSMC’s A14 production plan points to 2028

TSMC announced A14 on April 23, 2025, with production planned for 2028. In July 2026, DigiTimes reported that TSMC described development as on schedule, with risk production planned for 2027 and volume production for 2028. The first-half 2028 mass-production timing is a more specific schedule detail that Wccftech attributed to DigiTimes.

What the reported SRAM target would mean

A bit cell is the circuit unit that stores one bit in SRAM. TSMC’s published 2nm-CMOS-nanosheet design gives a high-density SRAM bit cell an area of 0.021 μm² and reports SRAM density of 38.1 Mb/mm². Wccftech, citing ETNews, reported a future A14 target below 0.017 μm².

Using 0.017 μm² as the cutoff, the calculation is (0.021 − 0.017) ÷ 0.021 ≈ 19.0%. A target below that cutoff would mean a reduction of more than roughly 19% in bit-cell area, if achieved.

That calculation applies to the bit cells themselves. An SRAM macro is the complete memory block, including supporting circuitry beyond its bit cells, so its total area depends on more than the bit-cell footprint.