Tom’s Hardware reported on October 23, 2026, that Micron’s G11 3D NAND roadmap calls for wafer-on-wafer bonding and more than 400 NAND layers, with a production ramp planned for the second half of 2027. The reported density, I/O and energy figures are company targets, not measured results.
What Micron’s G11 roadmap says
Micron’s reported targets for G11 include a 3D TLC NAND bit density of about 42 Gb/mm², I/O speeds of up to 5,400 MT/s, and more than 25% lower energy per transferred bit. Bit density measures how many bits fit in a given area; I/O speed describes the rate of data transfer. Micron’s reported I/O figure is up to 50% higher than its current-generation NAND.
Scott DeBoer, Micron’s president and chief technology and products officer, described the scaling plan as combining more layers with smaller cell dimensions. The reported roadmap also identifies high-capacity client and data-center SSDs, along with emerging AI-oriented storage devices, as intended applications.
Why wafer-on-wafer bonding matters
Micron plans to fabricate the NAND array and its peripheral logic and I/O on separate wafers, then bond the wafers together. Scott DeBoer said Micron considered this approach timely because it could be cost-effective and provide capabilities suited to G11’s product specifications.
Wafer-to-wafer bonding is one way to assemble components. Technical reviews describe potential gains in throughput and a simpler process flow, while noting that the economics depend on consistently high wafer yields. Die-to-wafer or die-to-die assembly can instead allow manufacturers to select known-good dies.
Why taller NAND stacks are hard to manufacture
In 3D NAND flash, memory layers are built vertically, and channel holes are etched through the stack. Lam Research’s general manufacturing explainer says etching those holes becomes more difficult as stacks grow, with additional challenges emerging beyond 200 layers. It also describes stack stress that can bow a wafer by hundreds of microns and backside stress-compensation material used to flatten it. These are general manufacturing challenges, not a description of Micron’s G11 process.
Wafer bonding and TSVs do different jobs
Wafer bonding describes how components are assembled. A through-silicon via, or TSV, is a vertical electrical connection through silicon. The approaches are not mutually exclusive: bonded wafers can also use TSVs, while die-to-die and die-to-wafer assembly are other integration options.
Micron targets a 2027 production ramp
Micron’s reported plan calls for G11 production to ramp in the second half of 2027. The company also plans to share further technical details in 2027, closer to high-volume manufacturing.
