Alibaba DAMO Academy announced the 64-bit XuanTie C950 on March 24, 2026, as server-oriented RISC-V processor IP for integration into larger systems. At an October 19 presentation, chief scientist Meng Jianyi shared later scaling and AI workload results. The presentation updated the story of a processor design, not a standalone consumer CPU.
What the October update added
Meng Jianyi presented C950 results at the RISC-V China Summit in Shenzhen. The reported figures included 78% XT-LINK multicore linearity at 128 cores and total performance 99.8 times the one-core reference.
The same presentation coverage reported inference rates of 43 tokens per second for Qwen3.8-Flash-Next and 38 tokens per second for DeepSeek V4-Flash. Those rates apply to the named models. The 128-core scaling figures describe a particular reported configuration, not every possible C950 implementation.
The C950 is configurable processor IP
RISC-V is an open instruction-set architecture, or ISA: a set of rules that defines how software communicates with a processor. C950 is a specific 64-bit implementation of that architecture, designed to be integrated into a larger system. Its datasheet describes an eight-wide, superscalar, out-of-order core. In an out-of-order design, the processor can execute ready instructions before earlier instructions that are waiting on data. The launch announcement also described a 16-stage pipeline and an instruction window exceeding 1,000 instructions.
The datasheet lists these configuration options:
| Component | Documented detail | Configuration or condition |
| Core | Eight-wide instruction decode; superscalar, out-of-order design | The launch announcement also cited a 16-stage pipeline and an out-of-order window exceeding 1,000 instructions |
| XuanTie TPE | Optional tensor-processing coprocessor using AME v0.5; up to 8 TOPS per TPE | TOPS means trillion operations per second; TPE is an optional block, not part of every C950 configuration |
| Vector datapath | Dual 256-bit datapaths | Vector Extension v1.0 and Vector Crypto are listed |
| L1 data cache | 64 KB, four-way, four-cycle load-to-use latency | Per-core cache detail |
| L2 cache | 256 KB to 3 MB | Configurable private cache per core |
| L3 cache | 0 to 8 MB | Optional, depending on interconnect configuration |
| XL-300 cluster | One to eight cores | Configurable cluster size |
| Interconnect | AMBA CHI.E or CHI.F in direct-connect mode; AXI4.0 or ACE4.0 ports in multicore mode | Direct-connect data width is 256 bits |
These options describe processor IP that system designers can configure. They are not a single fixed set of specifications for a retail processor. A TPE can accelerate supported tensor workloads, while the C950 core and its cache and interconnect options define other parts of a system design.
How to read the reported performance figures
The October presentation paired a 128-core result with a one-core reference: 99.8 times the reference and 78% multicore linearity. Linearity describes how closely performance scales with the number of cores compared with ideal scaling. Together, the figures describe reported XT-LINK scaling at that 128-core configuration.
The inference numbers are separate, model-specific results. Qwen3.8-Flash-Next was reported at 43 tokens per second, and DeepSeek V4-Flash at 38 tokens per second. A token rate for one named model is not a general throughput figure for other models or workloads.
Linux, QEMU, FPGA and TRACE32 in development
The reported C950 SDK stack lists Linux 6.6.36, OpenSBI 1.7, U-Boot 2024.10, QEMU 5.4.3, GCC 3.4.1 and LLVM 2.4.2. The XuanTie QEMU guide describes booting Linux 6.6 on an emulated eight-core C950 model. QEMU emulates a system in software, so that example is a route for software development rather than a physical eight-core processor demonstration.
Canonical separately demonstrated Ubuntu server virtualization with IOMMU on a C950 FPGA platform. An FPGA prototype is a hardware development platform; that demonstration and the QEMU software model are distinct development routes. Lauterbach TRACE32 support for C950 was also reported for simultaneous multicore debugging and non-intrusive trace capture, including high-speed off-chip trace transfer.
