At the sixth RISC-V China Summit, held in Shenzhen from October 18 to 20, David Patterson argued in a recorded presentation that RISC-V’s formal specification, customizability and modularity make it a strong fit for AI hardware design. He called it the only commercially viable instruction-set architecture (ISA) for that purpose, a position reported by EET China. NeoTeo’s preview of the summit covers the event’s schedule; the technical proposals Patterson discussed include an unfinished matrix-extension effort and a proposed memory design for some AI inference data.
Patterson’s case for RISC-V in AI
An ISA is the set of instructions a processor is designed to execute. Patterson’s argument, as reported by EET China, is that a clear, formal specification gives AI tools a defined target when helping design hardware; customizability leaves room for new instructions, while modularity lets designers choose components that are practical to implement and verify.
He contrasts RISC-V’s openness and flexibility with the licensing models and more closed architectures he associates with x86 and Arm. This is an architectural and commercial argument, not a measured performance ranking: Patterson’s reported claim does not amount to a head-to-head AI benchmark showing RISC-V ahead of either architecture.
What the IME project plans for vector registers
RISC-V International describes the Integrated Matrix Extension (IME) as a design effort intended to build on vector extensions and operate on existing vector registers. The project plans to evaluate alternative approaches using architectural and microarchitectural measures across embedded, application and high-performance computing (HPC) cores before selecting one. RISC-V International’s IME project page describes the work as an evaluation and selection process, rather than a finished extension.
That scope matters because matrix instructions need to fit real processor designs, from embedded cores to HPC systems. Reusing existing vector registers is part of the planned approach; the final design depends on which alternative the project selects.
EET China’s account of Patterson’s presentation names four matrix-acceleration routes: Zvbdot, IME, VME and AME. It orders them by how much additional state they introduce beyond RISC-V Vector (RVV), from least to most. The account says none of those proposals had been ratified as of October 2025 and reports that the VME task group was formally authorized in 2026.
AI number formats are an ecosystem task
Patterson’s presentation covered floating-point formats used in computing, including FP64, FP32, FP16 and BF16, as well as FP8 formats E5M2 and E4M3. It also mentioned industry discussion of FP6 and FP4. His point was that RISC-V implementations need software and instruction support for the numeric formats used in AI; the presentation’s format list does not mean every format is supported by every processor.
Why Patterson proposes HBF for some inference data
Patterson proposed high-bandwidth flash (HBF), a design that stacks flash memory alongside an application-specific integrated circuit (ASIC), for large, sparse data that is read often and written less frequently. The examples in the reported proposal include model weights, retrieval-augmented generation (RAG) knowledge bases and precomputed key-value (KV) cache. He also described retaining some standard DRAM for KV-cache use while placing other large, read-mostly data on HBF.
The proposed fit comes with tradeoffs. EET China reports that Patterson described HBF as having longer read latency, limited write endurance and restricted write performance. It accesses data in pages, such as 4 KB, rather than in cache-line-sized units. Those characteristics make the proposal specific to certain read-heavy workloads, rather than a general-purpose replacement for DRAM.
Patterson’s broader priorities for RISC-V include standardizing matrix extensions without fragmenting the ecosystem, supporting AI number formats, completing software support for AI and HBF, and using AI to help design and verify hardware. The IME project’s planned evaluation of competing approaches is one part of that standards work.
