Micron reportedly targets 1δ DRAM production in the second half of 2027

Micron reportedly has 1δ DRAM in yield ramp and targets high-volume production in the second half of 2027. The company expects the node’s bit density to improve by the mid-20% range over 1γ. Later planar and 3D DRAM remain development programs, while a separate 512 GB DDR5 server-module demonstration offers a product milestone alongside the process roadmap.

Micron’s near-term DRAM target is 1δ

Micron’s 1γ node is reported to be in high-volume manufacturing and is its first DRAM node to use EUV lithography. The next node, 1δ, is in yield ramp, with high-volume production targeted for the second half of 2027. The expected mid-20% bit-density increase over 1γ is a roadmap target, not an achieved result.

Micron plans to manufacture 1δ in the United States for next-generation DDR and LPDDR, graphics memory, HBM5, vertical HBM, and vertical Edge Inference Memory (vEIM). Those applications do not have individual production dates in the reported roadmap.

Planar scaling continues as 3D DRAM develops

Micron’s reported planar direction continues with 6F² cells after the company abandoned its 4F² plans. The later planar nodes are at earlier stages: 1ε is under development with wafer bonding planned; ζÅ is in early development, with High-NA EUV planned; and ηÅ is at the pathfinding stage.

Micron is also developing two 3D DRAM programs, 3D1 and 3D2. The company’s stated approach is to introduce 3D DRAM when its cost and performance can compete with planar memory. The programs have no reported production timetable or detailed architecture description.

AI memory plans target different workloads

Micron’s HBM plans include standard and custom products. Custom HBM is expected to begin with HBM4E, and a custom base die could incorporate logic tailored to a customer. For vertical HBM, Micron plans to stack memory directly over an ASIC or CPU rather than beside the processor on an interposer. Higher bandwidth is a design goal; power delivery and heat dissipation remain engineering challenges. Planned responses include hybrid bonding, heat spreaders, and thermal-aware design.

The first-generation vEIM targets edge inference, with about 2 TB/s of bandwidth and less than 1 picojoule of transfer energy per bit. Those figures are roadmap targets. Separately, Micron expects LPDDR6 to use about 35% less power than LPDDR5 and is developing DDR6 with a target of twice DDR5’s bandwidth. Micron is also working with Meta on LPDDR6 for data-center applications.

A separate 512 GB DDR5 server-module demonstration

Micron reportedly demonstrated a 512 GB DDR5 registered DIMM (RDIMM) across multiple server platforms, at speeds up to 9,200 MT/s. Mass production is targeted for the second half of 2027.

A dual-socket server with 24 slots could use these modules for about 12 TB of memory capacity: 24 × 512 GB equals 12,288 GB, or roughly 12 TB.

G11 NAND adds context to the roadmap

Micron’s G11 3D NAND plan targets mass production in the second half of 2027, with more than 400 active layers compared with 276 for G9. The roadmap also calls for wafer-on-wafer bonding. For G11 3D TLC, the reported targets include roughly twice G9’s bit density, 50% higher I/O speed, and more than 25% lower energy per transferred bit.

Micron has also described two AI NAND concepts: SLC-based NAND aimed at high IOPS, and TSV-stacked NAND with a logic base die aimed at high bandwidth. For background on the G9-to-G11 transition, see NeoTeo’s earlier coverage.