OpenAI’s Jalapeño went from RTL to tape-out in nine months, Ho says

OpenAI hardware vice president Richard Ho says Jalapeño took nine months to move from initial register-transfer-level (RTL) design to tape-out, with AI tools assisting the engineers who designed the inference chip. Standard electronic design automation (EDA) tools remained part of the sign-off process.

Jalapeño’s reported nine-month design timeline

Jalapeño is a custom application-specific integrated circuit (ASIC) designed for large language model inference: running a trained model to generate outputs. Ho described the nine-month interval as the time from initial RTL design to tape-out, when a completed chip design is handed off for fabrication.

OpenAI and Broadcom announced Jalapeño on June 24, 2026, as an inference accelerator. Ho’s account of its design process adds a look at how AI fit into that engineering work.

AI assisted engineers; it did not replace the design team

Ho described a workflow that brought together OpenAI models, Codex, existing EDA tools and experienced engineers. AI was used during development and for writing and optimizing kernels—software routines that carry out computations on a processor. Engineers remained responsible for the design work and decisions.

That distinction matters: AI support was part of a larger engineering process, not a substitute for the people and tools involved in building and checking a chip.

Standard EDA flows remained part of sign-off

OpenAI continued to use standard EDA flows for sign-off, Ho said. These established tools and checks remained part of the process alongside AI-assisted work and engineering oversight.

The nine-month interval is not a schedule for every chip

Ho described a traditional timeline of roughly 18 months to two years, often for designs using existing intellectual property (IP) or a legacy architecture. Jalapeño’s reported interval was for a design from scratch, so the two figures reflect different starting conditions.

Ho did not promise another nine-month cycle. He said the time for future designs would depend on what the team was building and on technology readiness.

What Ho said about later Jalapeño generations

Ho described the second-generation ASIC as approaching tape-out and the third generation as in development. He said future tape-outs would depend on technology readiness and whether a new generation offered a meaningful improvement, rather than following a fixed calendar cadence.