On September 26, 2026, SemiAnalysis published a physical teardown of Intel Core Ultra 7 365, a Panther Lake processor. Its cross-sections, floorplan analysis and package measurements detail the sample’s Intel 18A transistors, power delivery and tile construction.
A physical teardown examines Panther Lake
SemiAnalysis says it dismantled the Core Ultra 7 365 and examined cross-sections, elemental maps, die images, floorplans and package construction. The findings describe specific structures in that sample, including how different tiles use different manufacturing processes.
Panther Lake splits work across process-specific tiles
The package described combines a compute tile, a GPU tile and an I/O tile on a passive base using Foveros-S. The reported process assignments differ by tile and GPU option:
| Tile or option | Process | Described configuration |
| Compute tile | Intel 18A | Both described compute-tile variants use this process |
| GT1 GPU option | Intel 3 | 4 Xe3 cores |
| GT2 GPU option | TSMC N3E | 12 Xe3 cores |
| I/O tile variants | TSMC N6 | Two variants: a 12-lane tile and a larger variant with 20 PCIe lanes |
RibbonFET and PowerVia separate transistor and power-routing work
In the sampled Intel 18A structures, RibbonFET uses four stacked horizontal nanosheets. SemiAnalysis counted three sheets in sampled Samsung SF2 MBCFET structures; the sheet widths also differ.
PowerVia routes power through a backside metal stack, separate from the frontside signal wiring. The teardown describes frontside M0–M14 signal wiring and backside BM0–BM5 power wiring. Nano-TSVs connect the backside network to local contacts. A sampled connection from the contact level to BM0 spans about 150 nm and is described as a molybdenum-lined tungsten nano-TSV.
What the 18A density comparison measures
SemiAnalysis’s Bohr representative-cell model found similar density for sampled Intel 18A compute logic and TSMC N3E GPU logic. The model combines a four-transistor NAND2 cell spanning three gate pitches with a 32-transistor scan flip-flop spanning 19 pitches, weighting the two cell types 60:40. In the same model, the sampled 18A example was 18.6% denser than the Intel 3 GPU example. Whole-die density also depends on cell mix and placement.
The teardown also compares sampled metal geometry: the Intel 18A P-core M0 line has 2.63 times the cross-sectional area per line of the sampled TSMC N3E vector-engine M0 line, or 1.84 times the area after normalizing by routing pitch. Larger conductors can reduce resistance while also adding capacitance. These are structural measurements; performance per watt and battery life are system-level measures.
The floorplan comparison with Lunar Lake puts Panther Lake’s P-core area nearly unchanged, while private P-core L2 cache grows from 2.5 MiB to 3 MiB. Shared P-core L3 cache is reported as 14.8% smaller.
Foveros-S links the tiles over a passive base
At a sampled compute-tile edge, SemiAnalysis measured local microbump spacing of about 25.24 µm and a feature width of 12.33 µm. The reported local spacing is finer than the 36 µm nominal Foveros-S pitch cited in the teardown.
