In Q2 2026, TSMC’s 3 nm process accounted for 30% of wafer revenue, compared with 33% for 5 nm. The age-aligned historical figures add context: 7 nm held a larger share than 3 nm at their sixth separately reported-quarter checkpoint.
TSMC’s Q2 2026 mix
Each percentage is the portion of TSMC’s wafer revenue attributed to a process generation. In the second quarter of 2026, 5 nm was at 33%, three percentage points ahead of 3 nm at 30%.
How the comparison works
The historical comparison follows each process node’s first six quarters as a separately reported line item. It lines up the generations by their reporting-quarter sequence, rather than by calendar year, so the checkpoints reflect the same reporting age for each node.
Shares at matched checkpoints
At the second checkpoint, 10 nm had the largest share among the four generations. By the sixth, 7 nm led, with a larger share than 3 nm at the same reporting age.
| Process node | Second separately reported quarter (% of wafer revenue) | Sixth separately reported quarter (% of wafer revenue) |
| 10 nm | 25% | 6% |
| 7 nm | 23% | 35% |
| 5 nm | 20% | 23% |
| 3 nm | 15% | 26% |
Why the ramps differed
The generations started from different manufacturing conditions and served changing product mixes. TSMC said more than 95% of tools were compatible between 10 nm and 7 nm, allowing 7 nm to build on manufacturing-platform learning from its predecessor.
The 5 nm transition followed a different path: TSMC planned extensive use of extreme ultraviolet lithography (EUV), in part to reduce process complexity, while 7 nm relied on much of the established 10 nm tool base.
The targeted applications shifted as well. 10 nm was strongly associated with performance-focused mobile products; 7 nm served mobile and high-performance computing (HPC); and 5 nm targeted mobile and HPC from the outset.
What “3 nm” means
“3 nm” identifies a process generation. It is not a literal measurement of every transistor feature.
