Nagare Labs describes Z2RAM as proposed oxide-semiconductor memory designed to sit directly above accelerator logic. For its first generation, the company projects 5× the bit density of 2 nm high-density SRAM, 14× DRAM access speed, and one-third the read energy of SRAM. A report published on October 26, 2026, described Z2RAM as being at the lab-prototype stage.
Nagare’s projected performance targets
Nagare labels all three Gen 1 figures as projections. They compare different properties against different types of memory:
| Metric | Nagare’s Gen 1 projection | Comparison baseline |
| Bit density | 5× | 2 nm high-density SRAM |
| Access speed | 14× | DRAM |
| Read energy | One-third as much | SRAM |
The density target concerns how many bits could fit in a given area. Access speed and read energy describe separate aspects of operation, so the ratios are not a single overall performance score.
How the proposed Z2RAM cell works
Nagare co-founder Suman Datta described a cell built from two transistors. It would store charge using the gate capacitance of the second transistor, rather than the separate passive capacitor used in a conventional DRAM cell. Nagare says the design is intended to allow non-destructive reads and infrequent refresh.
The proposed memory layers would be deposited directly over accelerator logic. That differs from HBM, whose memory stacks sit beside the compute logic and connect through an interposer. Nagare presents placing memory over the logic as a way to shorten the connection between them. The company also describes a planned manufacturing approach using standard 300 mm production-class tooling, DUV patterning and CMOS processes.
Development milestones Nagare reports
Nagare’s account of the research traces several stages before the prototype phase. The company says an amorphous-oxide, two-transistor gain cell was demonstrated in 2020. In 2024, it selected the core material and device structure and optimized device reliability. In 2025, it says, researchers experimentally demonstrated a memory bit cell and fabricated a four-layer transistor structure. Nagare also reports that long-term stability was shown in 2026.
Integration and reliability hurdles
The report published on October 26, 2026, described Nagare’s technology as lab prototypes and said the company was seeking an R&D fabrication partner. In that report, co-founder Shimeng Yu identified the lack of an established standard for integrating this type of memory with accelerators. He said a proprietary interface might be needed; he also pointed to AMD’s 3D V-Cache as a proprietary memory-stacking approach.
Datta described a separate reliability concern: atomic vacancies and effects involving very small numbers of electrons could shift a transistor’s threshold voltage enough to disturb a cell. Those issues would have to be addressed alongside the integration work.
The same report said Nagare had raised $5 million in seed funding. It also described company goals to sample working tiles within four years and reach production shipments within a decade.
